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#Memory master 64a0tqdxa mml pdf#
#Memory master 64a0tqdxa mml Offline#

In particular, MML circuits include a memory block, a logic block and a first plurality of output data paths that interconnect the memory block and the logic block. Merged Memory and Logic (MML) integrated circuits include data path width reducing circuits and methods that are responsive to a test mode signal. using direct memory access or using auxiliary access paths

G11C29/48- Arrangements in static stores specially adapted for testing by means external to the store, e.g.

testing during refresh, power-on self testing or distributed testing cell constructio details, timing of test signals

G11C29/04- Detection or location of defective memory elements, e.g.

#Memory master 64a0tqdxa mml Offline#

G11C29/00- Checking stores for correct operation Subsequent repair Testing stores during standby or offline operation.

238000000926 separation method Methods 0.000 description 1.

230000001276 controlling effect Effects 0.000 description 1.

230000005540 biological transmission Effects 0.000 description 1.

Assignors: KIM, GYU-HONG Application granted granted Critical Publication of US5926420A publication Critical patent/US5926420A/en Anticipated expiration legal-status Critical Status Expired - Lifetime legal-status Critical Current Links

ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). reassignment SAMSUNG ELECTRONICS CO., LTD. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Priority to KR1019970032669A priority Critical patent/KR100269299B1/en Priority to KR97-32669 priority Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd Assigned to SAMSUNG ELECTRONICS CO., LTD.

Original Assignee Samsung Electronics Co Ltd Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime Application number US09/001,865 Inventor Gyu-Hong Kim Current Assignee (The listed assignees may be inaccurate.

#Memory master 64a0tqdxa mml pdf#

Google Patents Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methodsĭownload PDF Info Publication number US5926420A US5926420A US09/001,865 US186597A US5926420A US 5926420 A US5926420 A US 5926420A US 186597 A US186597 A US 186597A US 5926420 A US5926420 A US 5926420A Authority US United States Prior art keywords integrated circuit mml mml integrated output data path Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US5926420A - Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methods US5926420A - Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methods